MX_8_1
entity mx8_1 is
Port ( input : in STD_LOGIC_VECTOR (7 downto 0);
selection : in STD_LOGIC_VECTOR (2 downto 0);
clk : in STD_LOGIC;
output : out STD_LOGIC);
end mx8_1;
architecture Behavioral of mx8_1 is
component mx4_1_with_select is
Port ( s1, s2, s3, s4 : in STD_LOGIC;
C : in STD_LOGIC_VECTOR (1 downto 0);
d : out STD_LOGIC);
end component mx4_1_with_select;
signal tmp_data : STD_LOGIC_VECTOR(1 downto 0);
begin
MX1: mx4_1_with_select PORT MAP (
s1 => input(0),
s2 => input(1),
s3 => input(2),
s4 => input(3),
C => selection(1 downto 0),
d => tmp_data(0)
);
MX2: mx4_1_with_select PORT MAP (
s1 => input(4),
s2 => input(5),
s3 => input(6),
s4 => input(7),
C => selection(1 downto 0),
d => tmp_data(1)
);
with selection(2) select
output <= tmp_data(0) when '0',
tmp_data(1) when others;
end Behavioral;
MX_TB
ENTITY mx8_1_tb IS
END mx8_1_tb;
ARCHITECTURE behavior OF mx8_1_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mx8_1
PORT(
input : IN std_logic_vector(7 downto 0);
selection : IN std_logic_vector(2 downto 0);
clk : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
--Inputs
signal input : std_logic_vector(7 downto 0) := (others => '0');
signal selection : std_logic_vector(2 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal output : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mx8_1 PORT MAP (
input => input,
selection => selection,
clk => clk,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
input <= "00001011";
selection <= "000";
wait for 100 ns;
selection <= "010";
wait for 100 ns;
selection <= "001";
wait for 100 ns;
selection <= "010";
wait for 100 ns;
input <= "00001000";
selection <= "011";
wait for 100 ns;
input <= "00010000";
selection <= "100";
wait for 100 ns;
input <= "11101111";
selection <= "100";
wait for 100 ns;
input <= "00100010";
selection <= "101";
wait for 100 ns;
input <= "10100010";
selection <= "110";
wait for 100 ns;
input <= "10000000";
selection <= "111";
wait for 100 ns;
wait;
end process;
END;
generátor parity:
entity parity_generator is
generic (width : positive := 64;
even : STD_LOGIC := '1');
Port ( input : in STD_LOGIC_VECTOR ((width-1) downto 0);
clk : in STD_LOGIC;
parity : out STD_LOGIC);
end parity_generator;
architecture Behavioral of parity_generator is
signal tmp_data : STD_LOGIC_VECTOR ((width-1) downto 0);
begin
tmp_data(0) <= input(0);
CALCULATE:
for i in 1 to (width-1) generate
tmp_data(i) <= tmp_data(i-1) xor input(i);
end generate CALCULATE;
parity <= not tmp_data(width-1) when even = '1' else tmp_data(width-1);
end Behavioral;
generátor parity TB:
ENTITY parity_generator_tb IS
END parity_generator_tb;
ARCHITECTURE behavior OF parity_generator_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT parity_generator
PORT(
input : IN std_logic_vector(63 downto 0);
clk : IN std_logic;
parity : OUT std_logic
);
END COMPONENT;
--Inputs
signal input : std_logic_vector(63 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal parity : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: parity_generator PORT MAP (
input => input,
clk => clk,
parity => parity
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period
;
-- insert stimulus here
input <= X"01_00_00_00_00_01_00_02";
wait for 100 ns;
input <= X"00_00_00_00_00_01_00_02";
wait for 100 ns;
input <= X"FF_FF_FF_FF_FF_FF_FF_FE";
wait for 100 ns;
input <= X"FF_FF_FF_FF_FF_FF_FF_FF";
wait for 100 ns;
input <= X"FF_FF_FF_FF_FF_FF_FF_01";
wait for 100 ns;
input <= X"00_00_00_00_00_01_00_02";
wait for 100 ns;
input <= X"00_01_00_FF_00_FF_00_11";
wait for 100 ns;
input <= X"00_11_00_FF_00_FF_00_11";
wait for 100 ns;
wait;
end process;
END;
priority encoder:
entity priority_encoder is
generic (width : positive := 4);
Port ( inputs : in STD_LOGIC_VECTOR ((width-1) downto 0);
priority : out STD_LOGIC_VECTOR (((width/2)-1) downto 0);
valid : out STD_LOGIC;
clk : in STD_LOGIC);
end priority_encoder;
architecture Behavioral of priority_encoder is
signal tmp_data : STD_LOGIC_VECTOR ((width-1) downto 0);
begin
tmp_data(0) <= inputs(0);
WIDE_OR:
for i in 1 to (width - 1) generate
tmp_data(i) <= tmp_data(i-1) or inputs(i);
end generate WIDE_OR;
valid <= tmp_data(width-1);
priority(1) <= inputs(3) or inputs(2);
priority(0) <= inputs(3) or ((not inputs(2)) and inputs(1));
end Behavioral;
priority encoder TB:
ENTITY priority_encoder_tb IS
END priority_encoder_tb;
ARCHITECTURE behavior OF priority_encoder_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT priority_encoder
PORT(
inputs : IN std_logic_vector(3 downto 0);
priority : OUT std_logic_vector(1 downto 0);
valid : OUT std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal inputs : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal priority : std_logic_vector(1 downto 0);
signal valid : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: priority_encoder PORT MAP (
inputs => inputs,
priority => priority,
valid => valid,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
inputs <= "0010";
wait for 100 ns;
inputs <= "0001";
wait for 100 ns;
inputs <= "0101";
wait for 100 ns;
inputs <= "1001";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
pren 8_3:
entity priority_encoder_8_to_3 is
Port ( input_vector_8 : in STD_LOGIC_VECTOR (7 downto 0);
clk2 : in STD_LOGIC;
output_vector_3 : out STD_LOGIC_VECTOR (2 downto 0);
priority_bit : out STD_LOGIC);
end priority_encoder_8_to_3;
architecture Behavioral of priority_encoder_8_to_3 is
component priority_encoder is
generic (width : positive := 4);
Port ( inputs : in STD_LOGIC_VECTOR ((width-1) downto 0);
priority : out STD_LOGIC_VECTOR (((width/2)-1) downto 0);
valid : out STD_LOGIC;
clk : in STD_LOGIC);
end component priority_encoder;
signal validH : STD_LOGIC;
signal validL : STD_LOGIC;
signal prioH : STD_LOGIC_VECTOR(1 downto 0);
signal prioL : STD_LOGIC_VECTOR(1 downto 0);
begin
PEH: priority_encoder PORT MAP (
inputs => input_vector_8(7 downto 4),
clk => clk2,
valid => validH,
priority => prioH
);
PEL: priority_encoder PORT MAP (
inputs => input_vector_8(3 downto 0),
clk => clk2,
valid => validL,
priority => prioL
);
priority_bit <= validH or validL;
output_vector_3(2) <= validH;
output_vector_3(1 downto 0) <= prioH(1 downto 0) when validH = '1' else prioL(1 downto 0);
end Behavioral;
pren 8_3 TB:
ENTITY priority_encoder_8_to_3_tb IS
END priority_encoder_8_to_3_tb;
ARCHITECTURE behavior OF priority_encoder_8_to_3_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT priority_encoder_8_to_3
PORT(
input_vector_8 : IN std_logic_vector(7 downto 0);
clk2 : IN std_logic;
output_vector_3 : OUT std_logic_vector(2 downto 0);
priority_bit : OUT std_logic
);
END COMPONENT;
--Inputs
signal input_vector_8 : std_logic_vector(7 downto 0) := (others => '0');
signal clk2 : std_logic := '0';
--Outputs
signal output_vector_3 : std_logic_vector(2 downto 0);
signal priority_bit : std_logic;
-- Clock period definitions
constant clk2_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: priority_encoder_8_to_3 PORT MAP (
input_vector_8 => input_vector_8,
clk2 => clk2,
output_vector_3 => output_vector_3,
priority_bit => priority_bit
);
-- Clock process definitions
clk2_process :process
begin
clk2 <= '0';
wait for clk2_period/2;
clk2 <= '1';
wait for clk2_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
input_vector_8 <= "01001010";
wait for 100 ns;
input_vector_8 <= "11001010";
wait for 100 ns;
input_vector_8 <= "00000001";
wait for 100 ns;
input_vector_8 <= "00000000";
wait for 100 ns;
input_vector_8 <= "00111100";
wait for 100 ns;
input_vector_8 <= "00000011";
wait for 100 ns;
input_vector_8 <= "00001011";
wait for 100 ns;
input_vector_8 <= "00000101";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
